Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging

Author:

Gupta Ruchika1,Kulkarni Vedika J.1,Jose John1,Nandi Sukumar1

Affiliation:

1. Indian Institute of Technology Guwahati, Guwahati, India

Funder

SERB Project

ISEA Project Phase II

Publisher

ACM

Reference17 articles.

1. Intel xeon phiTM coprocessor - The Architecture;Chrysos G.;Intel Whitepaper,2014

2. Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip

3. Z. Shi and A. Burns , " Real-time communication analysis for on-chip networks with wormhole switching," in Second ACM/IEEE International SymposiumonNetworks-on-Chip(nocs2008) . IEEE , 2008 ,pp. 161 -- 170 . Z. Shi and A. Burns, "Real-time communication analysis for on-chip networks with wormhole switching," in Second ACM/IEEE International SymposiumonNetworks-on-Chip(nocs2008). IEEE,2008,pp.161--170.

4. M. Podlesny , Networking Mechanisms for delay-sensitive applications . Washington University in St. Louis, 2009 . M. Podlesny, Networking Mechanisms for delay-sensitive applications. Washington University in St. Louis, 2009.

5. T. H. Boraten and A. K. Kodi , " Securing nocs against timing attacks with noninterference based adaptive routing," in 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) . IEEE , 2018 , pp. 1 -- 8 . T. H. Boraten and A. K. Kodi, "Securing nocs against timing attacks with noninterference based adaptive routing," in 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS). IEEE, 2018, pp. 1--8.

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