Fallout

Author:

Canella Claudio1,Genkin Daniel2,Giner Lukas1,Gruss Daniel1,Lipp Moritz1,Minkin Marina2,Moghimi Daniel3,Piessens Frank4,Schwarz Michael1,Sunar Berk3,Van Bulck Jo4,Yarom Yuval5

Affiliation:

1. Graz University of Technology, Graz, Austria

2. University of Michigan, Ann Arbor, MI, USA

3. Worcester Polytechnic Institute, Worcester, MA, USA

4. imec-DistriNet, KU Leuven, Leuven, Belgium

5. University of Adelaide & Data61, Adelaide, Australia

Funder

Austrian Research Promotion Agency (FFG) via the project ESPRESSO

National Science Foundation

Advanced Micro Devices (AMD)

Defense Advanced Research Projects Agency (DARPA)

Austrian Research Promotion Agency (FFG) via the K-project DeSSnet

Research Foundation -- Flanders (FWO)

European Research Council (ERC) under the European Union's Horizon 2020

Intel Corporation

Research Fund KU Leuven

Publisher

ACM

Reference79 articles.

1. Method and apparatus for performing a store operation;Abramson Jeffery M;US Patent,2002

2. Method and Apparatus for Dispatching and Executing a Load Operation to Memory;Abramson Jeffrey M;US Patent,1998

3. ARM Limited. 2018. Vulnerability of Speculative Processors to Cache Timing Side-Channel Mechanism. ARM Limited. 2018. Vulnerability of Speculative Processors to Cache Timing Side-Channel Mechanism.

4. Daniel J. Bernstein. 2004. Cache-Timing Attacks on AES. http://cr.yp.to/antiforgery/cachetiming-20050414.pdf Daniel J. Bernstein. 2004. Cache-Timing Attacks on AES. http://cr.yp.to/antiforgery/cachetiming-20050414.pdf

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