Cache side-channel attacks and time-predictability in high-performance critical real-time systems

Author:

Trilla David1,Hernandez Carles2,Abella Jaume2,Cazorla Francisco J.3

Affiliation:

1. Universitat Politècnica de Catalunya and BSC

2. Barcelona Supercomputing Center (BSC)

3. BSC and IIIA-CSIC

Funder

Spanish Ministry of Science and Innovation

Publisher

ACM

Reference28 articles.

1. J. Abella et al. 2015. WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness. In SIES. J. Abella et al. 2015. WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness. In SIES .

2. O. Aciicmez et al. 2011. Method and system for securing instruction caches using substantially random instruction mapping scheme. (Nov. 8 2011). http://www.google.tl/patents/US8055848 US Patent 8 055 848. O. Aciicmez et al. 2011. Method and system for securing instruction caches using substantially random instruction mapping scheme. (Nov. 8 2011). http://www.google.tl/patents/US8055848 US Patent 8 055 848.

3. I. Agirre et al. 2015. IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. In DSD. 10.1109/DSD.2015.26 I. Agirre et al. 2015. IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. In DSD. 10.1109/DSD.2015.26

4. V. Bene al. 1964. Optimal Rearrangeable Multistage Connecting Networks. In Bell System Technical Journal. V. Bene al. 1964. Optimal Rearrangeable Multistage Connecting Networks. In Bell System Technical Journal .

5. ARM. 2001. ARM920T Technical Reference Manual. ARM. 2001. ARM920T Technical Reference Manual .

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