Compiler-guided instruction-level clock scheduling for timing speculative processors-Reference-Cited by-同舟云学术

Compiler-guided instruction-level clock scheduling for timing speculative processors

Published:2018-06-24 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 55th Annual Design Automation Conference
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Author:

Fan Yuanbo¹,Jia Tianyu¹,Gu Jie¹,Campanoni Simone¹,Joseph Russ¹

Affiliation:

1. Northwestern University

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3195970.3196013

Reference19 articles.

1. A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range;Bowman K. A.;IEEE Journal of Solid-State Circuits,2016

2. Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems

3. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

4. Dan Ernst Nam Sung Kim Shidhartha Das Sanjay Pant Rajeev Rao Toan Pham Conrad Ziesler David Blaauw Todd Austin Krisztian Flautner Trevor Mudge Beal Ave and Ann Arbor. 2003. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. December (2003). Dan Ernst Nam Sung Kim Shidhartha Das Sanjay Pant Rajeev Rao Toan Pham Conrad Ziesler David Blaauw Todd Austin Krisztian Flautner Trevor Mudge Beal Ave and Ann Arbor. 2003. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. December (2003).

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