Routability-driven and fence-aware legalization for mixed-cell-height circuits

Author:

Li Haocheng1,Chow Wing-Kai2,Chen Gengjie1,Young Evangeline F. Y.1,Yu Bei1

Affiliation:

1. CUHK

2. Cadence Design System Inc.

Funder

Research Grants Council, University Grants Committee

Publisher

ACM

Reference21 articles.

1. D. D. Sherlekar "Cell architecture for increasing transistor size " Jan. 14 2014 uS Patent 8 631 374. D. D. Sherlekar "Cell architecture for increasing transistor size " Jan. 14 2014 uS Patent 8 631 374.

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1. Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

2. A Fast Optimal Double-row Legalization Algorithm;ACM Transactions on Design Automation of Electronic Systems;2023-09-08

3. Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

4. Hybrid-Row-Height Design Placement Legalization Considering Cell Variants;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

5. RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

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