A type-safe arbitrary precision arithmetic portability layer for HLS tools-Reference-Cited by-同舟云学术

A type-safe arbitrary precision arithmetic portability layer for HLS tools

Published:2019 Issue: Volume: Page:
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Container-title:Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019
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Author:

Forget Luc¹,Uguen Yohann¹,de Dinechin Florent¹,Thomas David²

Affiliation:

1. Univ Lyon, INSA Lyon, Inria, CITI, Villeurbanne, France

2. Imperial College London, United Kingdom

Publisher

ACM Press

Reference13 articles.

1. Vivado Design Suite User Guide: High-Level Synthesis (UG902). https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug902-vivado-high-level-synthesis.pdf, 2018.

2. S. Bansal, H. Hsiao, T. Czajkowski, and J. H. Anderson. High-level synthesis of software-customizable floating-point cores. In 2018 Design, Automation & Test in Europe, pages 37--42. IEEE, 2018.

3. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. H. Anderson, S. Brown, and T. Czajkowski. LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In ACM/SIGDA international symposium on Field-Programmable Gate Arrays, pages 33--36, 2011.

4. J. O. Coplien. Curiously recurring template patterns. C++ Report, 7(2):24--27, 1995.

5. F. de Dinechin and B. Pasca. Designing custom arithmetic data paths with FloPoCo. IEEE Design & Test of Computers, 28(4):18--27, July 2011.

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