Catnap

Author:

Das Reetuparna1,Narayanasamy Satish1,Satpathy Sudhir K.1,Dreslinski Ronald G.1

Affiliation:

1. University of Michigan

Abstract

Multiple networks have been used in several processor implementations to scale bandwidth and ensure protocol-level deadlock freedom for different message classes. In this paper, we observe that a multiple-network design is also attractive from a power perspective and can be leveraged to achieve energy proportionality by effective power gating. Unlike a single-network design, a multiple-network design is more amenable to power gating, as its subnetworks (subnets) can be power gated without compromising the connectivity of the network. To exploit this opportunity, we propose the Catnap architecture which consists of synergistic subnet selection and power-gating policies. Catnap maximizes the number of consecutive idle cycles in a router, while avoiding performance loss due to overloading a subnet. We evaluate a 256-core processor with a concentrated mesh topology using synthetic traffic and 35 applications. We show that the average network power of a power-gating optimized multiple-network design with four subnets could be 44% lower than a bandwidth equivalent single-network design for an average performance cost of about 5%.

Funder

National Science Foundation

Division of Computing and Communication Foundations

Publisher

Association for Computing Machinery (ACM)

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fused Functional Units for Area-Efficient CGRAs;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. Improving power and performance of on-chip network through virtual channel sharing and power gating;Integration;2023-11

4. Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC;The Journal of Supercomputing;2023-05-07

5. DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks;Proceedings of the Great Lakes Symposium on VLSI 2022;2022-06-06

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