A soft error vulnerability analysis framework for Xilinx FPGAs-Reference-Cited by-同舟云学术

A soft error vulnerability analysis framework for Xilinx FPGAs

Published:2014-02-26 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Author:

Sari Aitzan¹,Agiakatsikas Dimitris¹,Psarakis Mihalis¹

Affiliation:

1. University of Piraeus, Piraeus, Greece

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2554688.2554767

Reference15 articles.

1. Altera 2010. Benchmark Designs For The Quartus University Interface Program (QUIP) Version 1.1 https://www.altera.com/support/software/download/altera_design/quip/quip-download.jsp. Altera 2010. Benchmark Designs For The Quartus University Interface Program (QUIP) Version 1.1 https://www.altera.com/support/software/download/altera_design/quip/quip-download.jsp.

2. Soft error rate estimation and mitigation for SRAM-based FPGAs

3. FPGA challenges and opportunities at 40nm and beyond

4. Betz V. and Rose J. 1997. VPR: a new packing placement and routing tool for FPGA research 213--222. Betz V. and Rose J. 1997. VPR: a new packing placement and routing tool for FPGA research 213--222.

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