NOrec

Author:

Dalessandro Luke1,Spear Michael F.2,Scott Michael L.1

Affiliation:

1. University of Rochester, Rochester, NY, USA

2. Lehigh University, Bethlehem, PA, USA

Abstract

Drawing inspiration from several previous projects, we present an ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusually clean semantics. While unlikely to scale to hundreds of active threads, this "NOrec" system offers many appealing features: very low fast-path latency--as low as any system we know of that admits concurrent updates; publication and privatization safety; livelock freedom; a small, constant amount of global metadata, and full compatibility with existing data structure layouts; no false conflicts due to hash collisions; compatibility with both managed and unmanaged languages, and both static and dynamic compilation; and easy acccommodation of closed nesting, inevitable (irrevocable) transactions, and starvation avoidance mechanisms. To the best of our knowledge, no extant STM system combines this set of features. While transactional memory for processors with hundreds of cores is likely to require hardware support, software implementations will be required for backward compatibility with current and near-future processors with 2--64 cores, as well as for fall-back in future machines when hardware resources are exhausted. Our experience suggests that NOrec may be an ideal candidate for such a software system. We also observe that it has considerable appeal for use within the operating system, and in systems that require both closed nesting and publication safety.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

Cited by 58 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. PIM-STM: Software Transactional Memory for Processing-In-Memory Systems;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

2. Short Paper: An Efficient Framework for Supporting Nested Transaction in STMs;Lecture Notes in Computer Science;2024

3. CSMV: A highly scalable multi-versioned software transactional memory for GPUs;Journal of Parallel and Distributed Computing;2023-10

4. On the impact of mode transition on phased transactional memory performance;Journal of Parallel and Distributed Computing;2023-03

5. HyTM-AP Hybrid Transactional Memory Scheme Using Abort Prediction and Adaptive Retry Policy for Multi-Core In-Memory Databases;Journal of Database Management;2022-06-29

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