Affiliation:
1. University of Wisconsin---Madison
Abstract
We develop an availability solution, called
SafetyNet,
that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At an abstract level,
SafetyNet
logically maintains multiple, globally consistent checkpoints of the state of a shared memory multiprocessor (i.e., processors, memory, and coherence permissions), and it recovers to a pre-fault checkpoint of the system and re-executes if a fault is detected.
SafetyNet
efficiently coordinates checkpoints across the system in logical time and uses "logically atomic" coherence transactions to free checkpoints of transient coherence state.
SafetyNet
minimizes performance overhead by pipelining checkpoint validation with subsequent parallel execution.We illustrate
SafetyNet
avoiding system crashes due to either dropped coherence messages or the loss of an interconnection network switch (and its buffered messages). Using full-system simulation of a 16-way multiprocessor running commercial workloads, we find that
SafetyNet
(a) adds statistically insignificant runtime overhead in the common-case of fault-free execution, and (b) avoids a crash when tolerated faults occur.
Publisher
Association for Computing Machinery (ACM)
Cited by
28 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Novel Fast Recovery Method for HT Tamper in Embedded Processor;Blockchain Technology and Emerging Technologies;2023
2. Bounded DBM-based clock state construction for timed automata in Uppaal;International Journal on Software Tools for Technology Transfer;2022-09-08
3. Reliability-Aware Runahead;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04
4. Efficient selective replication of critical code regions for SDC mitigation leveraging redundant multithreading;The Journal of Supercomputing;2021-05-10
5. Compiler-support for Critical Data Persistence in NVM;ACM Transactions on Architecture and Code Optimization;2020-01-10