Identifying the sources of cache misses in Java programs without relying on hardware counters

Author:

Inoue Hiroshi1,Nakatani Toshio1

Affiliation:

1. IBM Research - Tokyo, Tokyo, Japan

Abstract

Cache miss stalls are one of the major sources of performance bottlenecks for multicore processors. A Hardware Performance Monitor (HPM) in the processor is useful for locating the cache misses, but is rarely used in the real world for various reasons. It would be better to find a simple approach to locate the sources of cache misses and apply runtime optimizations without relying on an HPM. This paper shows that pointer dereferencing in hot loops is a major source of cache misses in Java programs. Based on this observation, we devised a new approach to identify the instructions and objects that cause frequent cache misses. Our heuristic technique effectively identifies the majority of the cache misses in typical Java programs by matching the hot loops to simple idiomatic code patterns. On average, our technique selected only 2.8% of the load and store instructions generated by the JIT compiler and these instructions accounted for 47% of the L1D cache misses and 49% of the L2 cache misses caused by the JIT-compiled code. To prove the effectiveness of our technique in compiler optimizations, we prototyped object placement optimizations, which align objects in cache lines or collocate paired objects in the same cache line to reduce cache misses. For comparison, we also implemented the same optimizations based on the accurate information obtained from the HPM. Our results showed that our heuristic approach was as effective as the HPM-based approach and achieved comparable performance improvements in the SPECjbb2005 and SPECpower_ssj2008 benchmark programs.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories;ACM Transactions on Computer Systems;2021-11-30

2. Panthera: holistic memory management for big data processing over hybrid memories;Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation;2019-06-08

3. Type Information Elimination from Objects on Architectures with Tagged Pointers Support;IEEE Transactions on Computers;2018-01-01

4. Efficient Management for Hybrid Memory in Managed Language Runtime;Lecture Notes in Computer Science;2016

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