Design space exploration of FinFET cache

Abstract

Integration of cache on-chip has significantly improved the performance of modern processors. The relentless demand for ever-increasing performance has led to the need to increase the cache capacity and number of cache levels. However, the performance improvement is accompanied by an increase in chip's power dissipation, requiring the use of more expensive cooling technologies to ensure chip reliability and long product life. The emergence of FinFETs as the technology of choice for high-performance computing poses new challenges to processor designers. With the introduction of new features in FinFETs, for example, independently controllable back gates, researchers have proposed several innovative memory cells that can reduce leakage power significantly, making the integration of a larger cache more practical. In this article, we comprehensively evaluate and compare the performance, power consumption (both dynamic and leakage), area, and temperature of different FinFET SRAM caches by exploring common configurations with varying cache size, block size, associativity, and number of banks. We evaluate caches based on four well-known FinFET SRAM cells: Pass-Gate FeedBack (PGFB), Row-based Back-Gate Biasing (RBGB), 8T, and 4T. We show how the caches can be simulated at self-consistent temperatures (at which leakage and temperature are in equilibrium). Drowsy and decay caches are two well-known leakage reduction techniques. We implement them in the context of FinFET caches to investigate their impact. We show that the RBGB cell-based cache is far superior in leakage and Power-Delay Product (PDP) to those based on the other three cells, sometimes by an order of magnitude. This superiority is maintained even when drowsy or decay leakage reduction techniques are applied to caches based on the other three cells, but not to the one based on the RBGB cell. This significantly diminishes the importance of drowsy or decay cache techniques, at least when the RBGB cell is used.