Author:
Deokar Rahul B.,Sapatnekar Sachin S.
Cited by
6 articles.
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1. A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
2. A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
3. The Stratix™ 10 Highly Pipelined FPGA Architecture;Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2016-02-21
4. Variables bounding based retiming algorithm;Journal of Computer Science and Technology;2002-11
5. Integration of retiming with architectural floorplanning;Integration;2000-03