A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)
Author:
Affiliation:
1. Tokyo Institute of Technology, Tokyo, Japan
2. Poco a poco networks Inc., Osaka, Japan
3. Hokkaido University, Hokkaido, Japan
Publisher
ACM
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1. Simulation of Fault Diagnosis Model for Managing Aeronautical Multivariate Heterogeneous Inputs;2023 International Conference on Pattern Recognition, Machine Vision and Intelligent Algorithms (PRMVIA);2023-03
2. Optimizing Neural Networks for Efficient FPGA Implementation: A Survey;Archives of Computational Methods in Engineering;2021-01-11
3. An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration;2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2020-06
4. Evaluating the performance of face sketch generation using generative adversarial networks;Pattern Recognition Letters;2019-12
5. [DL] A Survey of FPGA-based Neural Network Inference Accelerators;ACM Transactions on Reconfigurable Technology and Systems;2019-03-31
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