Affiliation:
1. University of Utah, Salt Lake City, UT
2. Cornell University, Ithaca, NY
Abstract
The advent of the system-on-chip and intellectual property hardware design paradigms makes protocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally intended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the development of the language, an evaluation of the language's utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Reference127 articles.
1. Accellera Organization Inc. 2002. SystemVerilog 3.0: Accellera's Extensions to VerilogTM. Accellera Organization Inc. Napa CA.]] Accellera Organization Inc. 2002. SystemVerilog 3.0: Accellera's Extensions to VerilogTM. Accellera Organization Inc. Napa CA.]]
2. Accellera Organization Inc. 2003. Property Specification Language Reference Manual. Accellera Organization Inc. Napa CA.]] Accellera Organization Inc. 2003. Property Specification Language Reference Manual. Accellera Organization Inc. Napa CA.]]
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