Structure of a multiprocessor using microprogrammable building blocks

Abstract

This paper describes a general purpose, microprogrammable, hardware building block called an Interpreter, an LSI-multiprocessing system in which the Interpreter is used, and a machine structure, implemented via firmware on the Interpreter. The Interpreter consists of five types of functional modules, each partitioned for eventual implementation with LSI arrays of 450-750 gates and less than 126 signal pins. One of these functional units is the writable microprogram memory, whose contents define the function of the Interpreter. The flexibility of the Interpreter is typified by its present use as a device controller, a stand-alone emulator of other machines, and as a multiprocessor. The Interpreter's main design concept allows functions formerly performed by software alone to be now performed by the emulating hardware. In this presentation an instruction set, which includes those software functions frequently and consistently used in operating systems, is emulated. The order code will allow for easy table and list manipulation or handling since much of scheduling and resource handling is confined to such operations. The ability to write code independent of the data to be processed is provided by accessing information through descriptions. These descriptions can locate the requested information, describe its structure, impose controls on the use of the information and provide signals to the operating system for special functions.