More Is Less: Model Augmentation for Intermittent Deep Inference

Author:

Kang Chih-Kai1ORCID,Mendis Hashan Roshantha2ORCID,Lin Chun-Han3ORCID,Chen Ming-Syan4ORCID,Hsiu Pi-Cheng5ORCID

Affiliation:

1. Academia Sinica and National Taiwan University, Taipei, Taiwan

2. Academia Sinica, Taipei, Taiwan

3. National Taiwan Normal University, Taipei, Taiwan

4. National Taiwan University and Academia Sinica, Taipei, Taiwan

5. Academia Sinica, National Taiwan University, and National Chi Nan University, Nantou, Taiwan

Abstract

Energy harvesting creates an emerging intermittent computing paradigm but poses new challenges for sophisticated applications such as intermittent deep neural network (DNN) inference. Although model compression has adapted DNNs to resource-constrained devices, under intermittent power, compressed models will still experience multiple power failures during a single inference. Footprint-based approaches enable hardware-accelerated intermittent DNN inference by tracking footprints, independent of model computations, to indicate accelerator progress across power cycles. However, we observe that the extra overhead required to preserve progress indicators can severely offset the computation progress accumulated by intermittent DNN inference. This work proposes the concept of model augmentation to adapt DNNs to intermittent devices. Our middleware stack, JAPARI, appends extra neural network components into a given DNN, to enable the accelerator to intrinsically integrate progress indicators into the inference process, without affecting model accuracy. Their specific positions allow progress indicator preservation to be piggybacked onto output feature preservation to amortize the extra overhead, and their assigned values ensure uniquely distinguishable progress indicators for correct inference recovery upon power resumption. Evaluations on a Texas Instruments device under various DNN models, capacitor sizes, and progress preservation granularities show that JAPARI can speed up intermittent DNN inference by 3× over the state of the art, for common convolutional neural architectures that require heavy acceleration.

Funder

Ministry of Science and Technology, Taiwan

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

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