A Methodology for Fault-Tolerant Pareto-Optimal Approximate Designs of FPGA-based Accelerators

Abstract

Approximate Computing Techniques (ACTs) take advantage of resilience computing applications to trade off between output precision, area, power and performance. ACTs can lead to significant gains at affordable costs when efficiently implemented on FPGA-based accelerators. Although several novel ACTs works have been proposed for FPGA accelerators, their applicability to high-assurance systems has not been explored as much. ACTs are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency. However, an important question comes to mind when targeting critical systems; Does ACT optimisation negatively affect the reliability of the system, and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy (TMR) with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability? This work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation in the design. In a nutshell, our DSE methodology has formulated the DSE with a Multi-Objective Optimization Problem (MOP). Each Pareto-optimal solution of our tool finds which arithmetic units of the design to implement with precise and approximate circuits and which units to selectively triplicate to remove single points of failure that compromise system reliability below acceptable thresholds. We also suggest another formulation of the DSE into a Single-Objective constraint Optimisation Problem (ScOP) producing a single optimal point, and that the user may demand, as a less time-consuming alternative to the MOP, if a complete Pareto-front is not needed. Our methodology generates fault-tolerant versions of the Pareto-optimal approximate designs (POADs) (or simple Optimised approximate designs (OADs) if the ScOP choice is picked) by selectively applying mitigation techniques in a way that the overheads of redundant resources for fault-tolerance do not negate the gains of approximation in comparison to the fault-tolerant versions of the precise design. We evaluate our method on two FPGA-based accelerators: a JPEG encoder and an H.264/AVC decoder. Our experimental results show significant gains in area, frequency and power consumption without compromising output quality and system reliability compared to classic solutions that replicate all or a part of the resources of the precise design to increase dependability metrics.