Affiliation:
1. Huazhong University of Science and Technology, Wuhan, Hubei, China
Abstract
Response Time Analysis (RTA) is an effective method for testing the schedulability of real-time tasks on multiprocessor platforms. Existing RTAs for global fixed priority scheduling calculate the upper bound of the worst case response time of each task. Given a target task, existing RTAs first calculate the workload upper bound of each higher priority task (than the target task), and then calculate the interference on the target task by each higher priority task according to the obtained workload upper bounds. The workload of a task consists of three parts: carry-in, body and carry-out. The interference from all these three parts may be overestimated in existing RTAs. However, although the overestimation of the interference from body is the major factor that causes the low accuracy of existing RTAs, all existing work only focuses on how to reduce the overestimation of the interference from carry-in, and there is no method to reduce the overestimation of the interference from body or carry-out. In this work, we propose a method to calculate the lower bound of the accumulative time in which the target task and higher priority tasks are executed in parallel. By excluding the parallel execution time from the interference, we derive a new RTA test that can reduce the overestimation of the interference from all three parts of the workload. Extensive experiments are conducted to verify the superior performance of the proposed RTA test.
Funder
National Natural Science Foundation of China
Fundamental Research Funds for the Central Universities
Hubei Provincial Natural Science Foundation of China
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
Cited by
2 articles.
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1. A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway;ACM Transactions on Design Automation of Electronic Systems;2024-09-04
2. Priority Assignment for Global Fixed Priority Scheduling on Multiprocessors;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-09