Author:
Blake Geoffrey,Dreslinski Ronald G.,Mudge Trevor
Cited by
35 articles.
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1. LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27
2. On the interactions between ILP and TLP with hardware transactional memory;Microprocessors and Microsystems;2024-02
3. Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory;2022 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP);2022-03
4. Transaction-Based Core Reliability;2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2020-05
5. Transactional pre-abort handlers in hardware transactional memory;Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques;2018-11