Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies-Reference-Cited by-同舟云学术

Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies

Published:2021-09-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Eight Annual ACM International Conference on Nanoscale Computing and Communication
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Author:

Bamberg Lennart¹,Krishna Tushar²,Joseph Jan Moritz³

Affiliation:

1. GrAI Matter Labs, Eindhoven, The Netherlands

2. Georgia Institute of Technology, Atlanta, GA, USA

3. RWTH Aachen University, Aachen, Germany

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3477206.3477457

Reference26 articles.

1. [n.d.]. Xilinx 3D IC portfolio. https://www.xilinx.com/products/silicon-devices/3dic.html. (Accessed on 06/13/2021). [n.d.]. Xilinx 3D IC portfolio. https://www.xilinx.com/products/silicon-devices/3dic.html. (Accessed on 06/13/2021).

2. A.B. Ahmed etal 2012. LA-XYZ: Low Latency High Throughput Look-Ahead Routing Algorithm for 3D-NoC Architecture. In MCSoC. A.B. Ahmed et al. 2012. LA-XYZ: Low Latency High Throughput Look-Ahead Routing Algorithm for 3D-NoC Architecture. In MCSoC.

3. B. Gopireddy etal 2019. Designing Vertical Processors in Monolithic 3D. In ISCA. B. Gopireddy et al. 2019. Designing Vertical Processors in Monolithic 3D. In ISCA.

4. D.U. Becker and W.J. Dally. 2009. Allocator implementations for network-on-chip routers. In IEEE SC. 1--12. D.U. Becker and W.J. Dally. 2009. Allocator implementations for network-on-chip routers. In IEEE SC. 1--12.

5. B.K. Joardar etal 2017. 3D NoC-enabled heterogeneous manycore architectures for accelerating CNN training: Performance and thermal trade-offs. In NOCS. B.K. Joardar et al. 2017. 3D NoC-enabled heterogeneous manycore architectures for accelerating CNN training: Performance and thermal trade-offs. In NOCS.