Field-testing IMPACT EPIC research results in Itanium 2

Author:

Sias John W.1,Ueng Sain-zee1,Kent Geoff A.1,Steiner Ian M.1,Nystrom Erik M.1,Hwu Wen-mei W.1

Affiliation:

1. University of Illinois at Urbana-Champaign

Abstract

Explicitly-Parallel Instruction Computing (EPIC) providesarchitectural features, including predication and explicitcontrol speculation, intended to enhance the compiler'sability to expose instruction-level parallelism (ILP) incontrol-intensive programs. Aggressive structural transformationsusing these features, though described in theliterature, have not yet been fully characterized in completesystems. Using the Intel Itanium 2 microprocessor,the SPECint2000 benchmarks and the IMPACT Compilerfor IA-64, a research compiler competitive with thebest commercial compilers on the platform, we providean in situ evaluation of code generated using aggressive,EPIC-enabled techniques in a reality-constrained microarchitecture.Our work shows a 1.13 average speedup(up to 1.50) due to these compilation techniques, relativeto traditionally-optimized code at the same inlining andpointer analysis levels, and a 1.55 speedup (up to 2.30) relativeto GNU GCC, a solid traditional compiler. Detailedresults show that the structural compilation approach providesbenefits far beyond a decrease in branch mispredictionpenalties and that it both positively and negatively impactsinstruction cache performance. We also demonstratethe increasing significance of runtime effects, such as datacache and TLB, in determining end performance and theinteraction of these effects with control speculation.

Publisher

Association for Computing Machinery (ACM)

Reference28 articles.

1. {1} D. Carmean "The Pentium 4 processor." Hot Chips 13 Stanford University Palo Alto CA August 2001. {1} D. Carmean "The Pentium 4 processor." Hot Chips 13 Stanford University Palo Alto CA August 2001.

2. {2} Intel Corporation Intel Itanium 2 Processor Reference Manual for Software Development Document Number 251110-001 June 2002. {2} Intel Corporation Intel Itanium 2 Processor Reference Manual for Software Development Document Number 251110-001 June 2002.

3. {3} J. Bharadwaj K. Menezes and C. McKinsey "Wavefront scheduling: Path based data representation and scheduling of subgraphs " in Proceedings of 32nd Annual International Symposium on Microarchitecture December 1999. {3} J. Bharadwaj K. Menezes and C. McKinsey "Wavefront scheduling: Path based data representation and scheduling of subgraphs " in Proceedings of 32nd Annual International Symposium on Microarchitecture December 1999.

4. The Intel IA-64 compiler code generator

5. The superblock: An effective technique for VLIW and superscalar compilation

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3