Low-Latency Virtual-Channel Routers for On-Chip Networks

Abstract

The on-chip communication requirements of manysystems are best served through the deployment of a regularchip-wide network. This paper presents the design of alow-latency on-chip network router for such applications.We remove control overheads (routing and arbitrationlogic) from the critical path in order to minimise cycle-timeand latency. Simulations illustrate that dramatic cycle timeimprovements are possible without compromising routerefficiency. Furthermore, these reductions permit flits to berouted in a single cycle, maximising the effectiveness of therouter's limited buffering resources.