Author:
Mukherjee Shyamapada,Roy Suchismita
Reference21 articles.
1. C. Ababei, H. Mogal, and K. Bazargan. Three-dimensional place and route for fpgas. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 25(6):1132--1140, 2006.
2. H. Arslan and S. Dutt. Road: An order-impervious optimal detailed router for fpgas. In 21st International Conference on Computer Design (ICCD 2003), VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pages 350--356. IEEE Computer Society, 2003.
3. H. Arslan and S. Dutt. An effective hop-based detailed router for fpgas for optimizing track usage and circuit performance. In Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pages 208--213. ACM, 2004.
4. V. Betz and J. Rose. Vpr: A new packing and placement and routing tool for fpga research. In Proceeding of 7th Annual Workshop Field Programmable Logic and Applications, pages 213--222, 1997.
5. S. Devadas. Optimal layout via boolean satisfiability. In Proceeding of the International Conference on Computer-Aided Design(ICCAD), pages 294--297. ACM/IEEE, November 1989.