Affiliation:
1. Technion-Israel Institute of Technology, Haifa, Israel
Abstract
Memory prefetchers are designed to identify and prefetch specific access patterns, including
spatiotemporal
locality (e.g., strides, streams), recurring patterns (e.g., varying strides, temporal correlation), and specific irregular patterns (e.g., pointer chasing, index dereferencing). However, existing prefetchers can only target premeditated patterns and relations they were designed to handle and are unable to capture access patterns in which they do not specialize. In this article, we propose a context-based neural network (NN) prefetcher that dynamically adapts to arbitrary memory access patterns. Leveraging recent advances in machine learning, the proposed NN prefetcher correlates program and machine contextual information with memory accesses patterns, using online-training to identify and dynamically adapt to unique access patterns exhibited by the code. By targeting
semantic locality
in this manner, the prefetcher can discern the useful context attributes and learn to predict previously undetected access patterns, even within noisy memory access streams. We further present an architectural implementation of our NN prefetcher, explore its power, energy, and area limitations, and propose several optimizations. We evaluate the neural network prefetcher over SPEC2006, Graph500, and several microbenchmarks and show that the prefetcher can deliver an average speedup of 21.3% for SPEC2006 (up to 2.3×) and up to 4.4× on kernels over a baseline of PC-based stride prefetcher and 30% for SPEC2006 over a baseline with no prefetching.
Funder
Intel Collaborative Research Institute for Computational Intelligence
Israel Science Foundation
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
Reference61 articles.
1. AMD. 2016. The “Zen” Core Architecture. Retrieved from http:/www.amd.com/en-gb/innovations/software-technologies/zen-cpu. AMD. 2016. The “Zen” Core Architecture. Retrieved from http:/www.amd.com/en-gb/innovations/software-technologies/zen-cpu.
2. AnandTech. 2016. Hot Chips 2016: Exynos M1 Architecture Disclosed. Retrieved from http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed. AnandTech. 2016. Hot Chips 2016: Exynos M1 Architecture Disclosed. Retrieved from http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed.
Cited by
20 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Beyond Belady to Attain a Seemingly Unattainable Byte Miss Ratio for Content Delivery Networks;IEEE Transactions on Parallel and Distributed Systems;2024-11
2. PatternS: An intelligent hybrid memory scheduler driven by page pattern recognition;Journal of Systems Architecture;2024-08
3. A New Formulation of Neural Data Prefetching;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29
4. Caching and Prefetching for Improving ORAM Performance;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W);2024-06-24
5. Enabling Large Dynamic Neural Network Training with Learning-based Memory Management;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02