Integrated CPU and l2 cache voltage scaling using machine learning-Reference-Cited by-同舟云学术

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Integrated CPU and l2 cache voltage scaling using machine learning

Published:2007 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '07
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Author:

AbouGhazaleh Nevine,Ferreira Alexandre,Rusu Cosmin,Xu Ruibin,Liberato Frank,Childers Bruce,Mosse Daniel,Melhem Rami

Publisher

ACM Press

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation;Proceedings of the 2015 Symposium on International Symposium on Physical Design;2015-03-29

2. Multicopy Cache;ACM Transactions on Embedded Computing Systems;2014-12-15

3. Integrated CPU Cache Power Management in Multiple Clock Domain Processors;High Performance Embedded Architectures and Compilers

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