Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics

Author:

Kim Hyungjun1,Kim Taesu1,Kim Jinseok1,Kim Jae-Joon1

Affiliation:

1. POSTECH, South Korea, Gyeongsangbukdo, South Korea

Abstract

Artificial Neural Network computation relies on intensive vector-matrix multiplications. Recently, the emerging nonvolatile memory (NVM) crossbar array showed a feasibility of implementing such operations with high energy efficiency. Thus, there have been many works on efficiently utilizing emerging NVM crossbar arrays as analog vector-matrix multipliers. However, nonlinear I-V characteristics of NVM restrain critical design parameters, such as the read voltage and weight range, resulting in substantial accuracy loss. In this article, instead of optimizing hardware parameters to a given neural network, we propose a methodology of reconstructing the neural network itself to be optimized to resistive memory crossbar arrays. To verify the validity of the proposed method, we simulated various neural networks with MNIST and CIFAR-10 dataset using two different Resistive Random Access Memory models. Simulation results show that our proposed neural network produces inference accuracies significantly higher than conventional neural network when the network is mapped to synapse devices with nonlinear I-V characteristics.

Funder

Ministry of Science and ICT

ICT Consilience Creative Program

Ministry of Trade, Industry 8 Energy

“Nano-Material Technology Development Program”

National Research Foundation of Korea

Industrial Technology Innovation Program

MSIT (Ministry of Science and ICT), Korea

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization;ACS Applied Materials & Interfaces;2024-01-01

2. Memristor-based LSTM neuromorphic circuits for offshore wind turbine blade fault detection;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. Resistive Neural Hardware Accelerators;Proceedings of the IEEE;2023-05

4. A-Connect: An Ex Situ Training Methodology to Mitigate Stochasticity in Neural Network Analog Accelerators;IEEE Transactions on Circuits and Systems I: Regular Papers;2023

5. XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

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