Co-optimizing memory-level parallelism and cache-level parallelism-Reference-Cited by-同舟云学术

Co-optimizing memory-level parallelism and cache-level parallelism

Published:2019-06-08 Issue: Volume: Page:
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Container-title:Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation
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Author:

Tang Xulong¹,Kandemir Mahmut Taylan¹,Karakoy Mustafa²,Arunachalam Meenakshi³

Affiliation:

1. Pennsylvania State University, USA

2. TOBB University of Economics and Technology, Turkey

3. Intel, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3314221.3314599

Reference60 articles.

1. Jennifer M. Anderson and Monica S. Lam. 1993. Global Optimizations for Parallelism and Locality on Scalable Parallel Machines. In PLDI. Jennifer M. Anderson and Monica S. Lam. 1993. Global Optimizations for Parallelism and Locality on Scalable Parallel Machines. In PLDI .

2. Nathan Binkert Bradford Beckmann Gabriel Black Steven K. Reinhardt Ali Saidi Arkaprava Basu Joel Hestness Derek R. Hower Tushar Krishna Somayeh Sardashti Rathijit Sen Korey Sewell Muhammad Shoaib Nilay Vaish Mark D. Hill and David A. Wood. 2011. The Gem5 Simulator. SIGARCH Computer. Architecture. News (2011). Nathan Binkert Bradford Beckmann Gabriel Black Steven K. Reinhardt Ali Saidi Arkaprava Basu Joel Hestness Derek R. Hower Tushar Krishna Somayeh Sardashti Rathijit Sen Korey Sewell Muhammad Shoaib Nilay Vaish Mark D. Hill and David A. Wood. 2011. The Gem5 Simulator. SIGARCH Computer. Architecture. News (2011).

3. Compiler optimizations for improving data locality

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