Efficient Virtual Memory Sharing via On-Accelerator Page Table Walking in Heterogeneous Embedded SoCs

Author:

Vogel Pirmin1,Kurth Andreas1,Weinbuch Johannes1,Marongiu Andrea2,Benini Luca2

Affiliation:

1. Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland

2. Integrated Systems Laboratory, ETH Zurich and Electrical, Electronic, and Information Engineering Department, University of Bologna, Bologna, Italy

Abstract

Shared virtual memory is key in heterogeneous systems on chip (SoCs) that combine a general-purpose host processor with a many-core accelerator, both for programmability and performance. In contrast to the full-blown, hardware-only solutions predominant in modern high-end systems, lightweight hardware-software co-designs are better suited in the context of more power- and area-constrained embedded systems and provide additional benefits in terms of flexibility and predictability. As a downside, the latter solutions require the host to handle in software synchronization in case of page misses as well as miss handling. This may incur considerable run-time overheads. In this work, we present a novel hardware-software virtual memory management approach for many-core accelerators in heterogeneous embedded SoCs. It exploits an accelerator-side helper thread concept that enables the accelerator to manage its virtual memory hardware autonomously while operating cache-coherently on the page tables of the user-space processes of the host. This greatly reduces overhead with respect to host-side solutions while retaining flexibility. We have validated the design with a set of parameterizable benchmarks and real-world applications covering various application domains. For purely memory-bound kernels, the accelerator performance improves by a factor of 3.8 compared with host-based management and lies within 50% of a lower-bound ideal memory management unit.

Funder

H2020 project HERCULES

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

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