Fault tolerance design for NoCs
Author:
Affiliation:
1. Kuwait University, Kuwait
Publisher
ACM Press
Reference9 articles.
1. Lehtonen, T. 2009. On fault tolerance methods for networks-on-chip. Turku Centre for Computer Science (TUCS), Finland, TURKU.
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3. Latif, K., Rahmani, A. M., Nigussie, E., Tenhunen, H., and Seceleanu, T. 2011. A novel topology-independent router architecture to enhance reliability and performance of Networks-on-Chip. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Vancouver, BC, 454--462.
4. Park, D., Nicopoulos, C., Kim, J., Vijaykrishnan, N., and Das, C. R. 2006. Exploring fault-tolerant network-on-chip architectures. In IEEE International Conference on Dependable Systems and Networks (DSN). Philadelphia, PA, 93--104.
5. Kang, Y. H., Kwon, T. J., and Draper, J. 2010. Fault-tolerant flow control in on-chip networks. In Fourth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), Washington, DC, USA, 79--86.
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1. Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip;ACM Transactions on Design Automation of Electronic Systems;2019-03-31
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