Using a Performance Model to Implement a Superscalar CVA6

Author:

Allart Côme1ORCID,Coulon Jean-Roch2ORCID,Sintzoff André2ORCID,Potin Olivier3ORCID,Rigaud Jean-Baptiste3ORCID

Affiliation:

1. Mines Saint-Étienne, CEA, Leti, Gardanne, France, Thales DIS, Meyreuil, France

2. Thales DIS, Meyreuil, France

3. Mines Saint-Étienne, CEA, Leti, Gardanne, France

Publisher

ACM

Reference11 articles.

1. EEMBC. 2024. Coremark. https://www.eembc.org/coremark/. (2024).

2. C. Allart et al. 2023. Performance Modeling of CVA6 with Cycle-Based Simulation. https://riscv-europe.org/summit/2023/posters.

3. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology

4. UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling

5. gem5. 2011. The gem5 simulator system. https://www.gem5.org/.

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