Identification of microprogrammable loops for problem oriented architecture synthesis

Abstract

The performance of a microprogrammable computer with the writable control memory can be improved by embedding a loop as a single microprogrammed instruction. This paper presents an algorithm for the identification of microprogrammable loops based on the construction of an interval. Also, implementation strategies are discussed with respect to such implementation phases as synthesis of a new instruction and its loading into the control memory. Finally, from the performance point of view, the problem oriented architecture synthesis is compared with the CPU operation overlap.