WCET-Aware Dynamic D-cache Locking for A Single Task

Author:

Zheng Wenguang1,Wu Hui1

Affiliation:

1. School of Computer Science and Engineering, The University of New South Wales

Abstract

Caches have been extensively used to bridge the increasing speed gap between processors and off-chip memory. However, caches make it much harder to compute the WCET (Worst-Case Execution Time) of a program. Cache locking is an effective technique for overcoming the unpredictability problem of caches. We investigate the WCET aware D-cache locking problem for a single task, and propose two dynamic cache locking approaches. The first approach formulates the problem as a global ILP (Integer Linear Programming) problem that simultaneously selects a near-optimal set of variables as the locked cache contents and allocates them to the D-cache. The second one iteratively constructs a subgraph of the CFG of the task where the lengths of all the paths are close to the longest path length, and uses an ILP formulation to select a near-optimal set of variables in the subgraph as the locked cache contents and allocate them to the D-cache. For both approaches, we propose a novel, efficient D-cache allocation algorithm. We have implemented both approaches and compared them with the longest path-based, dynamic cache locking approach proposed in [22] and the static WCET analysis approach without cache locking proposed in [14] by using a set of benchmarks from the Mälardalen WCET benchmark suite, SNU real-time benchmarks and the benchmarks used in [27]. Compared to the static WCET analysis approach, the average WCET improvements of the first approach range between 11.3% and 31.6%, and the average WCET improvements of the second approach range between 12.3% and 32.9%. Compared to the longest path-based, dynamic cache locking approach, the average WCET improvements of the first approach range between 4.7% and 14.3%, and the average WCET improvements of the second approach range between 5.3% and 15.0%.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

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Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Task Scheduling Algorithm for Minimizing Worst- Case Execution Time of Real-Time Embedded Systems;2021 International Conference on Computer Information Science and Artificial Intelligence (CISAI);2021-09

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