Affiliation:
1. School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
2. Department of ECE, Carnegie Mellon University, Pittsburgh, PA
Abstract
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.
Publisher
Association for Computing Machinery (ACM)
Reference28 articles.
1. Fast compilation for pipelined reconfigurable fabrics
2. D. Buell J. Arnold and E Athanas. SPLASH2: FPGAs in a custom computing machine. AW i96. D. Buell J. Arnold and E Athanas. SPLASH2: FPGAs in a custom computing machine. AW i96.
3. Managing pipeline-reconfigurable FPGAs
Cited by
28 articles.
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