Dynamic vectorization

Author:

Vajapeyam Sriram1,Joseph P. J.2,Mitra Tulika3

Affiliation:

1. Supercomputer Education and Research Centre and Dept. of Computer Science & Automation, Indian Institute of Science, Bangalore, India 560012

2. Dept. of Computer Science & Automation, Indian Institute of Science, Bangalore, India 560012

3. SUNY, Stony Brook and Dept. of Computer Science & Automation, Indian Institute of Science, Bangalore, India 560012

Abstract

Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynamic vectorization (DV), as a tool for quickly building up a large logical instruction window. Dynamic vectorization converts repetitive dynamic instruction sequences into vector form, enabling the processing of instructions from beyond the corresponding program loop to be overlapped with the loop. This enables vector-like execution of programs with relatively complex static control flow that may not be amenable to static, compile time vectorization. Experimental evaluation shows that a large fraction of the dynamic instructions of four of the six SPECInt92 programs can be captured in vector form. Three of these programs exhibit significant potential for ILP improvements from dynamic vectorization, with speedups of more than a factor of 2 in a scenario of realistic branch prediction and perfect memory disambiguation. Under perfect branch prediction conditions, a fourth program also shows well over a factor of 2 speedup from DV. The speedups are due to the overlap of post-loop processing with loop processing.

Publisher

Association for Computing Machinery (ACM)

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SIMT-X;ACM Transactions on Architecture and Code Optimization;2020-06-25

2. LPA: A First Approach to the Loop Processor Architecture;High Performance Embedded Architectures and Compilers

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