What to Lock?

Author:

Yasin Muhammad1,Sengupta Abhrajit1,Schafer Benjamin Carrion2,Makris Yiorgos2,Sinanoglu Ozgur3,Rajendran Jeyavijayan (JV)2

Affiliation:

1. New York University, Brooklyn, NY, USA

2. University of Texas at Dallas, Dallas, TX, USA

3. New York University Abu Dhabi, Abu Dhabi, Uae

Publisher

ACM

Reference18 articles.

1. "Defense Science Board (DSB) study on High Performance Microchip Supply " 2005 {March 16 2015}. {Online}. Available: www.acq.osd.mil/dsb/reports/ADA435563.pdf\ "Defense Science Board (DSB) study on High Performance Microchip Supply " 2005 {March 16 2015}. {Online}. Available: www.acq.osd.mil/dsb/reports/ADA435563.pdf\

2. Security against hardware Trojan through a novel application of design obfuscation

3. A Primer on Hardware Security: Models, Methods, and Metrics

4. SypherMedia "Syphermedia library " http://www.smi.tv/syphermedia_library_circuit_camouflage_technology.html {April 22 2016}. SypherMedia "Syphermedia library " http://www.smi.tv/syphermedia_library_circuit_camouflage_technology.html {April 22 2016}.

5. Split Manufacturing Method for Advanced Semiconductor Circuits;Jarvis R. W.;US Patent,2007

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1. Power Analysis Attack Against post-SAT Logic Locking schemes;2024 IEEE European Test Symposium (ETS);2024-05-20

2. CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09

3. KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

4. GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02

5. IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02

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