Performance pathologies in hardware transactional memory

Author:

Bobba Jayaram1,Moore Kevin E.1,Volos Haris1,Yen Luke1,Hill Mark D.1,Swift Michael M.1,Wood David A.1

Affiliation:

1. University of Wisconsin, Madison, WI

Abstract

Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously proposed HTMs represent three points in this design space: lazy conflict detection, lazy version management, committer wins (LL); eager conflict detection, lazy version management, requester wins (EL); and eager conflict detection, eager version management, and requester stalls with conservative deadlock avoidance (EE). To isolate the effects of these high-level design decisions, we develop a common framework that abstracts away differences in cache write policies, interconnects, and ISA to compare these three design points. Not surprisingly, the relative performance of these systems depends on the workload. Under light transactional loads they perform similarly, but under heavy loads they differ by up to 80%. None of the systems performs best on all of our benchmarks. We identify seven performance pathologies -interactions between workload and system that degrade performance-as the root cause of many performance differences: FriendlyFire, StarvingWriter, SerializedCommit, FutileStall, StarvingElder, RestartConvoy, and DuelingUpgrades. We discuss when and on which systems these pathologies can occur and show that they actually manifest within TM workloads. The insight provided by these pathologies motivated four enhanced systems that often significantly reduce transactional memory overhead. Importantly, by avoiding transaction pathologies, each enhanced system performs well across our suite of benchmarks.

Publisher

Association for Computing Machinery (ACM)

Cited by 51 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On the interactions between ILP and TLP with hardware transactional memory;Microprocessors and Microsystems;2024-02

2. LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager;IEEE Transactions on Parallel and Distributed Systems;2022-12-01

3. PfTouch: Concurrent page-fault handling for Intel restricted transactional memory;Journal of Parallel and Distributed Computing;2020-11

4. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory;IEEE Transactions on Parallel and Distributed Systems;2020-06-01

5. Transaction-Based Core Reliability;2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2020-05

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