Directive-Based, High-Level Programming and Optimizations for High-Performance Computing with FPGAs

Author:

Lambert Jacob1,Lee Seyong2,Kim Jungwon2,Vetter Jeffrey S.2,Malony Allen D.1

Affiliation:

1. University of Oregon

2. Oak Ridge National Laboratory

Funder

U.S. Department of Energy

Publisher

ACM

Reference25 articles.

1. {n. d.}. Intel FPGA SDK for OpenCL. https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html. {n. d.}. Intel FPGA SDK for OpenCL. https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html.

2. {n. d.}. Mentor - DK Design Suite. https://www.mentor.com/products/fpga/handel-c/dk-design-suite/. {n. d.}. Mentor - DK Design Suite. https://www.mentor.com/products/fpga/handel-c/dk-design-suite/.

3. {n. d.}. Xilinx - SDSoC Development Environment. https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html. {n. d.}. Xilinx - SDSoC Development Environment. https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html.

4. Using FPGA Devices to Accelerate Biomolecular Simulations

5. Amazon. {n. d.}. Amazon EC2 F1 Instances. ({n. d.}). https://aws.amazon.com/ec2/instance-types/f1/ Amazon. {n. d.}. Amazon EC2 F1 Instances. ({n. d.}). https://aws.amazon.com/ec2/instance-types/f1/

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1. High-Level Programming of FPGA-Accelerated Systems with Parallel Patterns;International Journal of Parallel Programming;2024-05-27

2. Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs;International Workshop on OpenCL;2021-04-27

3. FCNNLib: A Flexible Convolution Algorithm Library for Deep Learning on FPGAs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

4. Design and Preliminary Evaluation of OpenACC Compiler for FPGA with OpenCL and Stream Processing DSL;Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region Workshops;2020-01-15

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