Author:
Cunha Marcos,Fournel Nicolas,Pétrot Frédéric
Funder
Direction Générale de la Compétitivité, de l'Industrie et des Services
Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
Reference21 articles.
1. ARM. Embedded trace macrocell architecture specification. http://www.arm.com.
2. F. Bellard. QEMU, a fast and portable dynamic translator. InFREENIX, Anaheim, CA, 2005.
3. L. Cai and D. Gajski. Transaction level modeling: an overview. InProceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 19--24. ACM, 2003.
4. J. F. Cantin, M. H. Lipasti, and J. E. Smith. The complexity of verifying memory coherence. InProc. of the 2003 ACM Symp. on Parallel Algorithms and Architectures, 2003.
5. M. Gligor, N. Fournel, and F. Pétrot. Using binary translation in event driven simulation for fast and flexible MPSoC simulation. InProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, page 71--80, New York, NY, USA, 2009.
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