Affiliation:
1. The Chinese University of Hong Kong, Shatin, Hong Kong
Abstract
To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This article presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap, and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches,
Fast Median
approach,
LP
approach, and
Iterative
approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.
Funder
Research Grants Council of the Hong Kong Special Administrative Region, China
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Cited by
6 articles.
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