Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects-Reference-Cited by-同舟云学术

Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects

Published:2023-03-26 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2023 International Symposium on Physical Design
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Author:

Evmorfopoulos Nestor¹^ORCID,Shohel Mohammad Abdullah Al²^ORCID,Axelou Olympia¹^ORCID,Stoikos Pavlos¹^ORCID,Chhabria Vidya A.³^ORCID,Sapatnekar Sachin S.²^ORCID

Affiliation:

1. University of Thessaly, Volos, Greece

2. University of Minnesota, Minneapolis, MN, USA

3. Arizona State University, Tempe, AZ, USA

Funder

National Science Foundation

SPAWAR

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3569052.3578919

Reference46 articles.

1. J. Lienig "Electromigration and its impact on physical design in future technologies " in Proceedings of the International Symposium on Physical Design pp. 33--40 2013. J. Lienig "Electromigration and its impact on physical design in future technologies " in Proceedings of the International Symposium on Physical Design pp. 33--40 2013.

2. J. Lienig and M. Thiele , " The pressing need for electromigration-aware physical design," in Proceedings of the International Symposium on Physical Design , pp. 144 -- 151 , 2018 . J. Lienig and M. Thiele, "The pressing need for electromigration-aware physical design," in Proceedings of the International Symposium on Physical Design, pp. 144--151, 2018.

3. S. S. Sapatnekar , "Electromigration-aware interconnect design," in Proceedings of the International Symposium on Physical Design , pp. 83 -- 90 , 2019 . S. S. Sapatnekar, "Electromigration-aware interconnect design," in Proceedings of the International Symposium on Physical Design, pp. 83--90, 2019.

4. Circuit-level reliability requirements for Cu metallization

5. C. Auth etal "A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors self-aligned quad patterning contact over active gate and cobalt local interconnects " in IEEE International Electronic Devices Meeting pp. 29.1.1-29.1.4 2017. C. Auth et al. "A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors self-aligned quad patterning contact over active gate and cobalt local interconnects " in IEEE International Electronic Devices Meeting pp. 29.1.1-29.1.4 2017.