F4T: A Fast and Flexible FPGA-based Full-stack TCP Acceleration Framework

Author:

Boo Junehyuk12ORCID,Chung Yujin12ORCID,Baek Eunjin12ORCID,Na Seongmin1ORCID,Kim Changsu2ORCID,Kim Jangwoo12ORCID

Affiliation:

1. Seoul National University, Seoul, Republic of Korea

2. MangoBoost Inc., Seoul, Republic of Korea

Publisher

ACM

Reference48 articles.

1. 2013. The SO_REUSEPORT socket option. https://lwn.net/Articles/542629/. 2013. The SO_REUSEPORT socket option. https://lwn.net/Articles/542629/.

2. 2017. UltraScale Architecture Configurable Logic Block User Guide. https://docs.xilinx.com/v/u/en-US/ug574-ultrascale-clb. 2017. UltraScale Architecture Configurable Logic Block User Guide. https://docs.xilinx.com/v/u/en-US/ug574-ultrascale-clb.

3. 2019. HLS packet processing. https://github.com/Xilinx/HLS_packet_processing. 2019. HLS packet processing. https://github.com/Xilinx/HLS_packet_processing.

4. 2020. Checksum Offload. https://www.kernel.org/doc/html/latest/networking/checksum-offloads.html. 2020. Checksum Offload. https://www.kernel.org/doc/html/latest/networking/checksum-offloads.html.

5. 2020. Receive Side Scaling. https://www.kernel.org/doc/Documentation/networking/scaling.txt. 2020. Receive Side Scaling. https://www.kernel.org/doc/Documentation/networking/scaling.txt.

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