DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory-Reference-Cited by-同舟云学术

DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory

Published:2023-06-17 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 50th Annual International Symposium on Computer Architecture
language:
Short-container-title:

Author:

Jin Wenjing¹^ORCID,Jang Wonsuk¹^ORCID,Park Haneul¹^ORCID,Lee Jongsung¹²^ORCID,Kim Soosung¹^ORCID,Lee Jae W.¹^ORCID

Affiliation:

1. Seoul National University, Seoul, Republic of Korea

2. Samsung Electronics, Suwon, Republic of Korea

Funder

Samsung Electronics

Institute of Information & Communications Technology Planning & Evaluation (IITP) of Korea

Publisher

ACM

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5. Intel Memory Latency Checker v3.9a. https://www.intel.com/content/www/us/en/developer/articles/tool/intelr-memory-latency-checker.html. Intel Memory Latency Checker v3.9a. https://www.intel.com/content/www/us/en/developer/articles/tool/intelr-memory-latency-checker.html.

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