Hardware Trojan Detection Using Machine Learning: A Tutorial

Author:

Gubbi Kevin Immanuel1ORCID,Saber Latibari Banafsheh1ORCID,Srikanth Anirudh1ORCID,Sheaves Tyler1ORCID,Beheshti-Shirazi Sayed Arash2ORCID,PD Sai Manoj2ORCID,Rafatirad Satareh1ORCID,Sasan Avesta1ORCID,Homayoun Houman1ORCID,Salehi Soheil3ORCID

Affiliation:

1. University of California, Davis, California, USA

2. George Mason University, Fairfax, VA, USA

3. University of Arizona, Tucson, Arizona, USA

Abstract

With the growth and globalization of IC design and development, there is an increase in the number of Designers and Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no option but to use external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan (HT) . An HT can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fail to detect HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a Trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful in helping eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this tutorial, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN) -assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.

Funder

National Science Foundation

Computing Research Association for CIFellows

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Reference66 articles.

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