LLHD: a multi-level intermediate representation for hardware description languages-Reference-Cited by-同舟云学术

LLHD: a multi-level intermediate representation for hardware description languages

Published:2020-06-06 Issue: Volume: Page:
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Container-title:Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation
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Author:

Schuiki Fabian¹,Kurth Andreas¹,Grosser Tobias¹,Benini Luca¹

Affiliation:

1. ETH Zurich, Switzerland

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3385412.3386024

Reference27 articles.

1. IEEE 1076-2008. 2008. VHDL Language Reference Manual. IEEE 1076-2008. 2008. VHDL Language Reference Manual.

2. IEEE 1164. 1993. Standard Multivalue Logic System for VHDL Model Interoperability. IEEE 1164. 1993. Standard Multivalue Logic System for VHDL Model Interoperability.

3. IEEE 1364. 2005. Standard for Verilog Hardware Description Language. IEEE 1364. 2005. Standard for Verilog Hardware Description Language.

4. IEEE 1800-2017. 2017. SystemVerilog Unified Hardware Design Specification and Verification Language. IEEE 1800-2017. 2017. SystemVerilog Unified Hardware Design Specification and Verification Language.

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