Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform-Reference-Cited by-同舟云学术

Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform

Published:2019-08-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 48th International Conference on Parallel Processing: Workshops
language:
Short-container-title:

Author:

You Yi-Ping¹,Lin Tsung-Chun¹,Yang Wuu¹

Affiliation:

1. Department of Computer Science, College of Computer Science, National Chiao Tung University, Hsinchu, Taiwan

Funder

Ministry of Science and Technology, Taiwan

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3339186.3339192

Reference24 articles.

1. {n. d.}. musl. https://www.musl-libc.org/ {n. d.}. musl. https://www.musl-libc.org/

2. 2008. IEEE Standard for Floating-Point Arithmetic. IEEE Std 754-2008 (Aug 2008) 1--70. 2008. IEEE Standard for Floating-Point Arithmetic. IEEE Std 754-2008 (Aug 2008) 1--70.

3. ARM 2013. ARM® Architecture Reference Manual ARMv8 for ARMv8-A architecture profile. ARM. ARM 2013. ARM® Architecture Reference Manual ARMv8 for ARMv8-A architecture profile. ARM.

4. On Static Binary Translation of ARM/Thumb Mixed ISA Binaries

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient RISC-V-on-x64 Floating Point Simulation;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

2. Hyperchaining for LLVM-Based Binary Translators on the x86-64 Platform;Journal of Signal Processing Systems;2022-09-05

3. Lasagne: a static binary translator for weak memory model architectures;Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation;2022-06-09

4. Profile-guided optimisation for indirect branches in a binary translator;Connection Science;2022-02-19

5. Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms;50th International Conference on Parallel Processing Workshop;2021-08-09