Scalable Performance Prediction of Codes with Memory Hierarchy and Pipelines

Author:

Chennupati Gopinath1,Santhi Nandakishore1,Eidenbenz Stephan1

Affiliation:

1. Los Alamos National Laboratory, Los Alamos, NM, USA

Publisher

ACM

Reference37 articles.

1. Fog Agner. 2016. Instruction tables: Lists of instruction latencies throughputs and micro-operation breakdowns for Intel AMD and VIA CPUs. Technical University of Denmark Copenhagen Denmark. Fog Agner. 2016. Instruction tables: Lists of instruction latencies throughputs and micro-operation breakdowns for Intel AMD and VIA CPUs. Technical University of Denmark Copenhagen Denmark.

2. A Brief History of HPC Simulation and Future Challenges. In Proceedings of the 2017 Winter Simulation Conference (WSC '17);Ahmed Kishwar;IEEE,2017

3. An Integrated Interconnection Network Model for Large-Scale Performance Prediction

4. LogGP

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