1. Manuel J. Bellido-Díaz , Jorge Juan-Chico , and Manuel Valencia . 2006. Logic-Timing Simulation and the Degradation Delay Model . Imperial College Press , London . Manuel J. Bellido-Díaz, Jorge Juan-Chico, and Manuel Valencia. 2006. Logic-Timing Simulation and the Degradation Delay Model. Imperial College Press, London.
2. Spiking Neural Networks Hardware Implementations and Challenges
3. A new gate delay model for simultaneous switching and its applications
4. A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate
5. Arman Ferdowsi , Ulrich Schmid , and Josef Salzmann . 2022. An Accurate Hybrid Delay Model for Multi-Input Gates. arXiv preprint arXiv:2211.10628 ( 2022 ). Arman Ferdowsi, Ulrich Schmid, and Josef Salzmann. 2022. An Accurate Hybrid Delay Model for Multi-Input Gates. arXiv preprint arXiv:2211.10628 (2022).