Formal Techniques for Effective Co-verification of Hardware/Software Co-designs-Reference-Cited by-同舟云学术

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Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

Published:2017-06-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 54th Annual Design Automation Conference 2017
language:
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Author:

Mukherjee Rajdeep¹,Purandare Mitra²,Polig Raphael²,Kroening Daniel¹

Affiliation:

1. University of Oxford

2. IBM Research, Zurich

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3061639.3062253

Reference17 articles.

1. Automated firmware testing using firmware-hardware interaction patterns

2. Effective Preprocessing in SAT Through Variable and Clause Elimination

3. HW/SW co-verification of embedded systems using bounded model checking

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1. Hardware/software security co-verification and vulnerability detection: An information flow perspective;Integration;2024-01

2. A Resource Aware Memory Requirement Calculation Model for Memory Constrained Context-Aware Systems;IEEE Access;2024

3. Toward System-Level Assertions for Heterogeneous Systems;Advanced Boolean Techniques;2023

4. Versatile Binary-Level Concolic Testing;Handbook of Computer Architecture;2022

5. Verifizierung von eingebetteten Software-Binärdateien mit Hilfe virtueller Prototypen;Verbessertes virtuelles Prototyping;2022

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