A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era-Reference-Cited by-同舟云学术

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era

Published:2017-06-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 54th Annual Design Automation Conference 2017
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Author:

Wang Jian-Ping¹,Sapatnekar Sachin S.¹,Kim Chris H.¹,Crowell Paul¹,Koester Steve¹,Datta Supriyo²,Roy Kaushik²,Raghunathan Anand²,Hu X. Sharon³,Niemier Michael³,Naeemi Azad⁴,Chien Chia-Ling⁵,Ross Caroline⁶,Kawakami Roland⁷

Affiliation:

1. University of Minnesota

2. Purdue University

3. Notre Dame University

4. Georgia Tech

5. Johns Hopkins University

6. MIT

7. Ohio State University

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3061639.3072942

Reference71 articles.

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3. Proposal for an all-spin logic device with built-in memory

4. M. G. Mankalale etal 2016. CoMET: Composite-Input Magnetoelectric-based Logic Technology. arXiv: 1611.09714v2 IEEE J. Explor. Solid-State Comput. Devices Circuits M. G. Mankalale et al 2016. CoMET: Composite-Input Magnetoelectric-based Logic Technology. arXiv: 1611.09714v2 IEEE J. Explor. Solid-State Comput. Devices Circuits

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